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PA3FWM's software defined radio (SDR) page documents his extensive hardware and software development efforts between 2004 and 2009. Initial experiments utilized a direct conversion receiver with 90-degree phase difference, feeding a PC soundcard at 48 kHz sample rate, covering 24 kHz of spectrum around a 7080.5 kHz local oscillator. This setup, similar to AC50G's QEX 2002 article, allowed for basic I/Q signal processing to distinguish signals above and below the LO frequency. Limitations included fixed crystal frequencies, 16-bit dynamic range, and narrow bandwidth. Subsequent hardware iterations aimed for enhanced performance, incorporating external 24-bit ADCs with 192 kHz sample rates, connected via 10 Mbit/s Ethernet. A **MC145170-based PLL** and programmable octave divider provided a 58 kHz to 30 MHz tuning range. The **Tayloe mixer** was employed, with differential outputs feeding a PCM1804 ADC. An ATmega32 microcontroller handled serial data conversion to Ethernet frames, though without CRC calculation due to processing constraints. Later designs integrated AD7760 2.5 Msamples/second ADCs and a Xilinx Spartan-3 FPGA, enabling direct reception of 0-1 MHz spectrum and eventually 2.5 MHz bandwidth across the shortwave spectrum. Software was refactored to use an initial 8192 non-windowed FFT for efficient high-bandwidth processing. The project culminated in a two-way QSO on 21 MHz using the developed hardware and software, demonstrating transmit capabilities with a D/A converter. The system exhibited a 2.5 MHz wide spectrum display and a zoomed 19 kHz display, capturing signals like ionospheric chirp sounders and RTTY contest activity. Challenges included noise leakage from digital circuitry and cooling for high-power dissipation components.