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Catalogs a diverse array of Software Defined Radio (SDR) projects and realizations, systematically classified by their sampling methodologies and underlying hardware architectures. The resource delineates projects into categories such as those utilizing soundcard sampling of traditional transceiver audio outputs (Type Ia), mono soundcard sampling of intermediate frequencies (Type R1x-x-xx), stereo soundcard sampling of I/Q IFs (Type Q1x-x-xx), dedicated stereo audio ADC sampling of I/Q IFs (Type Q2x-x-xx), direct antenna RF signal sampling with off-the-shelf acquisition boards (Type R3x-x-xx), dedicated RF ADC sampling of analog IFs (Type R2x-x-xx), dedicated RF ADC sampling of direct antenna RF signals with ASIC-based processing (Type R4x-A-xx), FPGA-based processing (Type R4x-F-xx), and specialized IF chipsets combining ADC and DDC functions (Type Dxx-S-xx). Each entry provides a brief description, often including pricing, availability of source code, and specific hardware components like ADCs, DACs, DDS, and FPGAs. The compilation presents various practical applications, from PSK31 and Packet radio implementations to adaptations of the DRM standard for amateur radio bandwidths, such as Hamdream and WinDRM. It features specific hardware designs like the SoftRock-40 for the 40-meter band, the Firefly SDR for 30m and 40m, and more complex systems like the Quicksilver QS1R, which employs a 16-bit 130 Msamples/s ADC and an Altera Cyclone III FPGA. The resource also lists sample processing software, RF front-end designs, and academic/commercial SDR initiatives, offering insights into different approaches for I/Q conversion and digital signal processing in SDR systems.

PA3FWM's software defined radio (SDR) page documents his extensive hardware and software development efforts between 2004 and 2009. Initial experiments utilized a direct conversion receiver with 90-degree phase difference, feeding a PC soundcard at 48 kHz sample rate, covering 24 kHz of spectrum around a 7080.5 kHz local oscillator. This setup, similar to AC50G's QEX 2002 article, allowed for basic I/Q signal processing to distinguish signals above and below the LO frequency. Limitations included fixed crystal frequencies, 16-bit dynamic range, and narrow bandwidth. Subsequent hardware iterations aimed for enhanced performance, incorporating external 24-bit ADCs with 192 kHz sample rates, connected via 10 Mbit/s Ethernet. A **MC145170-based PLL** and programmable octave divider provided a 58 kHz to 30 MHz tuning range. The **Tayloe mixer** was employed, with differential outputs feeding a PCM1804 ADC. An ATmega32 microcontroller handled serial data conversion to Ethernet frames, though without CRC calculation due to processing constraints. Later designs integrated AD7760 2.5 Msamples/second ADCs and a Xilinx Spartan-3 FPGA, enabling direct reception of 0-1 MHz spectrum and eventually 2.5 MHz bandwidth across the shortwave spectrum. Software was refactored to use an initial 8192 non-windowed FFT for efficient high-bandwidth processing. The project culminated in a two-way QSO on 21 MHz using the developed hardware and software, demonstrating transmit capabilities with a D/A converter. The system exhibited a 2.5 MHz wide spectrum display and a zoomed 19 kHz display, capturing signals like ionospheric chirp sounders and RTTY contest activity. Challenges included noise leakage from digital circuitry and cooling for high-power dissipation components.

A 200 kHz bandwidth digital transmission system for image transfer in the Amateur Service is under development, specifically targeting VHF allocations. John B. Stephensen, KD6OZH, leads this project under an FCC Special Temporary Authority (STA) valid until September 10, 2006, authorizing emissions up to 200 kHz bandwidth in the 50.3-50.8 MHz segment. Current regulations typically limit bandwidths to 20 kHz on VHF amateur bands, making this STA crucial for testing wideband digital modes. The modem, a modified **OFDM** (Orthogonal Frequency Division Multiplexed) unit, was initially tested on the 70-cm band. It splits a high-rate data stream into multiple low-rate subcarriers to mitigate multipath echoes. The system uses a DCP-1 card with a Xilinx XC3S400 FPGA and Oki Semiconductor ML67Q5003 microcontroller. The transmitter, located at 36d 46m 30s N, 119d 46m 22s W, generates 150 WPEP into an 8 dBi gain vertical antenna, while the mobile receiver uses a Ham-stick. Three data formats for 50, 100, and 200 kHz channels are being tested, with encoded data rates of 96, 192, and 384 kbps. Verilog code for the VHF OFDM modem is 95% simulated, with modifications from the UHF version including increased filter coefficient precision and a change from Ungerboeck **TCM** to BICM for improved performance over fading paths. Final tests will involve one-way over-the-air measurements of bit error rates and coverage area.